The present invention relates to a processing unit of a computer and more particularly to an arithmetic-logic operation unit suitable for use in logic and arithmetic operations between data of one unit word length and between data of two unit word lengths.
In a prior art arithmetic-logic operation unit, as described in MOTOROLA's "MC68020 32-Bit Microprocessor User's Manual", Second Edition, PP. 1.3 to 2.1, there are provided an arithmetic logic unit of the word-length width required for processing data exceeding to unit word lengths, for example, that for processing data of two unit word lengths and registers for storing input data to and output data from the arithmetic logic unit. When data of smaller word length than the word length which the arithmetic logic unit is capable of processing is processed thereby, only the low-order side of the output data from the output of the arithmetic logic unit is stored in the register.
Thus, there has been a problem that, when data of half the storable word length of the register or less are processed, the storable word length of the register has not been effectively utilized, although it is capable of storing two data or more.